1. Field of the Invention
The present invention relates to a pulse width modulator for pulse-width modulating (PWM), for example, an audio signal and outputting the modulated signal, and a switching amplifier using the pulse width modulator.
2. Description of the Related Art
Conventionally, Japanese Patent Application Laid-Open No. 2010-273326 proposes, for example, a current-integrated pulse width modulator (hereinafter, simply referred to as “an integrated pulse width modulator”). The integrated pulse width modulator converts an amplitude of an audio signal (voltage signal) into an electric current, charges a capacitor with the electric current for a constant time, and discharges charged electric charges of the capacitor with the constant electric current so as to convert the audio signal into a pulse width modulation signal (hereinafter, referred to as “PWM signal”) whose pulse width is a discharging time of the capacitor.
FIG. 7 is a block diagram illustrating a basic circuit configuration of the integrated pulse width modulator disclosed in Japanese Patent Application Laid-Open No. 2010-273326. FIG. 8 is a diagram illustrating one example of concrete circuits of two pulse signal generation circuits and a pulse signal synthesizing circuit in the pulse width modulator.
An integrated pulse width modulator 100 includes a control signal generation circuit 101, a voltage to current converting circuit 102, four switching circuits SW1 to SW4, two integrators 103 and 104, one discharging circuit 105, two pulse signal generation circuits 106 and 107, and one pulse signal synthesizing circuit 108.
The integrated pulse width modulator 100 generates a PWM signal SPWM according to the following principal such that:    (1) an audio signal (voltage signal) is converted into an electric current is that changes in proportion to its amplitude;    (2) an operation for storing electric charges in the integrator 103 with the electric current is for a high-level duration of a reference clock in a period T and discharging the stored charges in the integrator 103 with a constant current Id for a low-level duration through the discharging circuit 105 is repeated, and the pulse signal generation circuit 106 generates a pulse signal S1 whose pulse width is a discharging time td at every time of a charge storage operation in the integrator 103;    (3) further, an operation for storing electric charges in the integrator 104 with the electric current is for the low-level duration of the reference clock in the period T and discharging the stored charges in the integrator 104 with the constant current Id for the high-level duration through the discharging circuit 105 is repeated, and the pulse signal generation circuit 107 generates a pulse signal S2 whose pulse width is a discharging time td at every time of a charge storage operation in the integrator 104; and    (4) the pulse signal synthesizing circuit 108 synthesizes the pulse signal S1 and the pulse signal S2 so that respective pulses of the pulse signal S1 and respective pulses of the pulse signal S2 are connected to each other alternately.
The control signal generation circuit 101 generates a control signal φ1 that is identical to the reference clock MCLK and a control signal φ2 obtained by inverting the level of the reference clock MCLK based on the reference clock MCLK having a predetermined period T. Further, the control signal generation circuit 101 outputs a set signal set1 obtained by detecting fall of the level of the control signal φ1 and a set signal set2 obtained by detecting fall of the level of the control signal φ2. The voltage to current converting circuit 102 is composed of, for example, a circuit for generating a difference voltage of an audio signal es with respect to a ground level through a differential amplifier circuit and converting the difference voltage into an electric current. The switching circuits SW1 to SW4 are composed of semiconductor switches such as bipolar transistors. The integrators 103 and 104 are composed of capacitors having the same capacity (see capacitors C1 and C2 in FIG. 8). The pulse signal generation circuits 106 and 107 are composed of a /RS flip-flop circuit (symbol “/” represents negative logic. Hereinafter, the much the same is true on the description about a flip-flop circuit.) that is composed of, for example, a NAND logic gate shown in FIG. 8 for inputting a set/reset signal based on a negative logic. The pulse signal synthesizing circuit 108 is composed of a NAND circuit shown in FIG. 8.
FIG. 9 is a time chart illustrating an operation for generating a PWM signal of the integrated pulse width modulator 100. In the time chart in FIG. 9, the switching circuits SW1 to SW4 perform an ON operation when the control signals φ1 to φ4 are at a high level, and perform an OFF operation at a low level. Further, the pulse signal generation circuits 106 and 107, and the pulse signal synthesizing circuit 108 are composed of a circuit shown in FIG. 8.
The control signals φ1 and φ2 shown in FIG. 9 are clocks whose period is the same as that of the reference clock generated by the control signal generation circuit 101 based on the reference clock MCLK. The control signal φ1 controls an ON/OFF operation of the switching circuit SW1, and the control signal φ2 controls an ON/OFF operation of the switching circuit SW3. A control signal φ3 is a signal outputted from a Q output of the pulse signal generation circuit (a /RS flip-flop circuit) 106, and controls an ON/OFF operation of the switching circuit SW2. A control signal φ4 is a signal outputted from a Q output of the pulse signal generation circuit (a /RS flip-flop circuit) 107, and controls an ON/OFF operation of the switching circuit SW4. The set signal set1 is a signal inputted into a /S input of the pulse signal generation circuit (the /RS flip-flop circuit) 106, and a signal obtained by detecting fall of the control signal φ1. Further, the set signal set2 is a signal inputted into a /S input of the pulse signal generation circuit (the /RS flip-flop circuit) 107, and a signal obtained by detecting fall of the control signal φ2.
A waveform of V1 represents a change in a both-end voltage V1 of the capacitor C1 caused by charging the capacitor C1 with an electric current is outputted from the voltage to current converting circuit 102 for a period in which the control signal φ1 is at the high level, and discharging the capacitor C1 with a constant electric current Id through the discharging circuit 105 for a low-level period. A waveform of V2 represents a change in a both-end voltage V2 of the capacitor C2 caused by charging the capacitor C2 with the electric current is outputted from the voltage-current converting circuit 102 for a period in which the control signal φ2 is at the high level, and discharging the capacitor C2 with the constant electric current Id through the discharging circuit 105 for a low-level period.
In pulse width modulation of the audio signal es, a reference level (0 V) of an amplitude fluctuation in the audio signal es is allocated to a modulation degree 0[%] of PWM signal SPWM. When the amplitude is larger than 0 V, a modulation degree m changes in proportion to the amplitude in a positive direction within a range of 0 to 100[%], and when the amplitude is smaller than 0 V, the modulation degree m changes in proportion to the amplitude in a negative direction within the range of 0 to 100 [%].
The electric current is outputted from the voltage to current converting circuit 102 is expressed by is=Io±k·|es|. When the amplitude of the audio signal es is 0 (no signal), an electric current I0 is outputted from the voltage to current converting circuit 102. The waveforms of V1 and V2 in FIG. 9 are waveforms when the amplitude of the audio signal es is 0 (no signal), and a discharge time td of the waveform of V1 and a discharge time td′ of the waveform of V2 are ½ of an OFF time t of the control signals φ1 and φ2. When the amplitude is larger than 0 V in the negative direction, the electric current is is such that is=Io−k·|es|. For this reason, waveforms of charge and discharge of the capacitors C1 and C2 are as illustrated by a broken line of the waveform of V1, and the discharge times td and td′ are shorter than t/2. On the contrary, when the amplitude is larger than 0 V in the positive direction, the electric current is is such that is=Io+k·|es|. For this reason, the waveforms of the charge and discharge of the capacitors C1 and C2 are as illustrated by an alternate long and short dash line of the waveform of V1, and the discharge times td and td′ are longer than t/2.
The pulse signal S1 is a signal outputted from a /Q output of the pulse signal generation circuit (the /RS flip-flop circuit) 106 shown in FIG. 8, and the control signal φ3 is a signal outputted from the Q output of the pulse signal generation circuit (the /RS flip-flop circuit) 106. When the low-level signal set1 detecting fall of the control signal φ1 is inputted into the /S input, the Q output of the pulse signal generation circuit (the /RS flip-flop circuit) 106 is inverted into the low level, and thereafter when the voltage V1 of the capacitor C1 is lowered into a reference voltage Vth (a voltage to be a reference at a charging start time of the capacitor C1) by discharge, the /Q output is inverted into the high level and maintain the high level until next input of the signal set1. For this reason, the pulse signal S1 has a rectangular wave in such that it is at the low level for the discharge time td of the capacitor C1.
Since the control signal φ3 is such that the level of the pulse signal S1 is inverted, it becomes a pulse signal that is at the high level for the discharge time td of the capacitor C1. Since the pulse signal generation circuit (the /RS flip-flop circuit) 107 also operates similarly to the pulse signal generation circuit (the /RS flip-flop circuit) 106, the pulse signal S2 has a rectangular wave such that it is at the low level for a discharge time td′ of the capacitor C2, and the control signal φ4 becomes a pulse signal that is at the high level for the discharge time td′ of the capacitor C2.
A PWM signal SPWM is a signal that is outputted from the pulse signal synthesizing circuit 108. Since the pulse signal synthesizing circuit 108 outputs a calculated result of NAND of the pulse signal S1 and the pulse signal S2, the pulse signal synthesizing circuit 108 outputs the PWM signal SPWM that is synthesized so that pulses of the pulse signal S1 and pulses of the pulse signal S2 are connected alternately. When the high-level period is denoted by T1 and the low-level period is denoted by T2, the modulation degree m of PWM signal SPWM is expressed by:m=|T1−T2|×100/(T1+T2)[%].
The integrated pulse width modulator 100 is configured so that when a common-mode noise or a distortion in a time axial direction occurs in a process that the PWM signal is generated from the audio signal es, an error component Δts caused by the noise or the distortion is directly generated.
The conventional integrated pulse width modulator 100 is configured so that both the two integrators 103 and 104 are charged with the same electric current is. For this reason, when a common-mode noise occurs and an error component Δis is mixed in the electric current is, both the pulse widths of the pulse signals S1 and S2 generated by the pulse signal generation circuits 106 and 107, respectively include an error Δts on basis of the error component Δis. Since the PWM signal SPWM is a NAND signal of the pulse signal S1 and the pulse signal S2, the error component Δts of the pulse signals S1 and S2 is superimposed on the modulation degree m of the PWM signal SPWM, and the PWM signal becomes a signal on which a common-mode noise or harmonics is superimposed.